Digital varactors can be used for a variety of applications in communications and signal processing. For example, digital phase locked loops (PLLs), such as those used for direct carrier frequency synthesis and modulation, may include a number of digital blocks. In some instances of a PLL, the forward path from the phase detector to the oscillator may include a digital loop filter and a digital varactor. Conventionally, a digital varactor can be used to carry out fine-tuning of the oscillator frequency. Additionally, in some systems, there may also be a need for synchronization of the varactor control data.
For controlling synchronization within a digital varactor, gated devices such as latches may be used. For example, the varactor frequency tuning range may typically include the modulation range and can also accommodate other oscillator frequency variations, such as for taking temperature drift into account. Thus, in the digital domain, the varactor needs a certain bit range, which, in a decimal counting scheme, can represent the number of varactor cells. The clock frequency of this digital signal can depend on the dedicated system requirements.
For linearity issues, the varactor cells through which the frequency stepping is carried out can be realized in thermometer-encoded design style. A second issue which can occur in the case of a large modulation bandwidth is that the number of switched thermometer-encoded bits per clock cycle is typically limited to a small number. The reason for this limitation is a high ratio of the clock frequency to the modulation step size per clock cycle, which results in the modulation being fairly low in frequency in comparison to the varactor clock frequency.
The number of latches (gated devices) used typically correlates to the number of individual varactors which are used in the digital varactor unit, which can be a relatively high number. Further, for each clock cycle, all the latches are typically driven with the same clock signal. The cycling of the latches with each clock signal can result in relatively high power consumption, with all the drawbacks that entails. On the other hand, only a small number of the varactors actually need to be switched during any specific clock cycle because of oversampling from the clock frequency with respect to the modulation bandwidth.
The inventor has determined that the conventional technique leads to unnecessarily high power consumption because all the latches are cycled with each clock cycle, even if there is no change in the data for a particular varactor cell from one cycle to the next. This high power consumption can cause large current peaks as a result of the charging and discharging activities due to the clock signal. Furthermore, such current peaks can create supply ripples and supply drops, which can disturb the oscillator signal. Additionally, with an increased number of latches and/or an increased clock frequency, the charge fluctuations will increase. Higher charge fluctuations will consequently cause higher supply currents, which can cause the supply ripples to also increase. Thus, one deleterious effect of the conventional technique is an increase in the spurious level at the oscillator output signal. A second detrimental effect of the conventional technique is that the overall power consumption is large, and increases as the number of latches increases. For example, one application of in which varactors may be implemented is for use in battery-powered cellular telephones, where it is desirable to lower power consumption whenever possible. A third undesirable effect is that a large supply ripple can distort the varactor array itself. This can degrade the PLL performance due to negative effects on the varactor's linearity.